Differential D584 Diff 1494 src/leveldb/port/atomic_pointer.h

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src/leveldb/port/atomic_pointer.h

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#define ARCH_CPU_PPC_FAMILY 1		#define ARCH_CPU_PPC_FAMILY 1
#elif defined(__mips__)		#elif defined(__mips__)
#define ARCH_CPU_MIPS_FAMILY 1		#define ARCH_CPU_MIPS_FAMILY 1
#endif		#endif

namespace leveldb {		namespace leveldb {
namespace port {		namespace port {

		// AtomicPointer based on <cstdatomic> if available
		#if defined(LEVELDB_ATOMIC_PRESENT)
		class AtomicPointer {
		private:
		std::atomic<void*> rep_;
		public:
		AtomicPointer() { }
		explicit AtomicPointer(void* v) : rep_(v) { }
		inline void* Acquire_Load() const {
		return rep_.load(std::memory_order_acquire);
		}
		inline void Release_Store(void* v) {
		rep_.store(v, std::memory_order_release);
		}
		inline void* NoBarrier_Load() const {
		return rep_.load(std::memory_order_relaxed);
		}
		inline void NoBarrier_Store(void* v) {
		rep_.store(v, std::memory_order_relaxed);
		}
		};

		#else

// Define MemoryBarrier() if available		// Define MemoryBarrier() if available
// Windows on x86		// Windows on x86
#if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)		#if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)
// windows.h already provides a MemoryBarrier(void) macro		// windows.h already provides a MemoryBarrier(void) macro
// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx		// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
#define LEVELDB_HAVE_MEMORY_BARRIER		#define LEVELDB_HAVE_MEMORY_BARRIER

// Mac OS		// Mac OS
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines	inline void* Acquire_Load() const {
return result;		return result;
}		}
inline void Release_Store(void* v) {		inline void Release_Store(void* v) {
MemoryBarrier();		MemoryBarrier();
rep_ = v;		rep_ = v;
}		}
};		};

// AtomicPointer based on <cstdatomic>
#elif defined(LEVELDB_ATOMIC_PRESENT)
class AtomicPointer {
private:
std::atomic<void*> rep_;
public:
AtomicPointer() { }
explicit AtomicPointer(void* v) : rep_(v) { }
inline void* Acquire_Load() const {
return rep_.load(std::memory_order_acquire);
}
inline void Release_Store(void* v) {
rep_.store(v, std::memory_order_release);
}
inline void* NoBarrier_Load() const {
return rep_.load(std::memory_order_relaxed);
}
inline void NoBarrier_Store(void* v) {
rep_.store(v, std::memory_order_relaxed);
}
};

// Atomic pointer based on sparc memory barriers		// Atomic pointer based on sparc memory barriers
#elif defined(__sparcv9) && defined(__GNUC__)		#elif defined(__sparcv9) && defined(__GNUC__)
class AtomicPointer {		class AtomicPointer {
private:		private:
void* rep_;		void* rep_;
public:		public:
AtomicPointer() { }		AtomicPointer() { }
explicit AtomicPointer(void* v) : rep_(v) { }		explicit AtomicPointer(void* v) : rep_(v) { }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	public:
inline void NoBarrier_Store(void* v) { rep_ = v; }		inline void NoBarrier_Store(void* v) { rep_ = v; }
};		};

// We have neither MemoryBarrier(), nor <atomic>		// We have neither MemoryBarrier(), nor <atomic>
#else		#else
#error Please implement AtomicPointer for this platform.		#error Please implement AtomicPointer for this platform.

#endif		#endif
		#endif

#undef LEVELDB_HAVE_MEMORY_BARRIER		#undef LEVELDB_HAVE_MEMORY_BARRIER
#undef ARCH_CPU_X86_FAMILY		#undef ARCH_CPU_X86_FAMILY
#undef ARCH_CPU_ARM_FAMILY		#undef ARCH_CPU_ARM_FAMILY
#undef ARCH_CPU_ARM64_FAMILY		#undef ARCH_CPU_ARM64_FAMILY
#undef ARCH_CPU_PPC_FAMILY		#undef ARCH_CPU_PPC_FAMILY

} // namespace port		} // namespace port
} // namespace leveldb		} // namespace leveldb

#endif // PORT_ATOMIC_POINTER_H_		#endif // PORT_ATOMIC_POINTER_H_