Differential D5662

Fix invalid use a memory order relaxed
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Authored by deadalnix on Apr 2 2020, 23:07.

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rSTAGING7df20faa1c55: Fix invalid use a memory order relaxed
rABC7df20faa1c55: Fix invalid use a memory order relaxed

Summary

It is self evident that these operation need to have a global order, or two thread may end up allocating the same id. Thankfully, the x86 memory model ensures that it won't happen, but I wouldn't bet as much on various flavour of ARM or other RISC CPUs.

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Read carefully, I guess...

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rABC Bitcoin ABC

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deadalnix created this revision.Apr 2 2020, 23:07

Herald added a reviewer: Restricted Project. · View Herald TranscriptApr 2 2020, 23:07

Build Bitcoin-ABC / Diffs / Diff Testing (build-diff) started.

Build Bitcoin-ABC / Diffs / Diff Testing (build-diff) passed.

Harbormaster completed remote builds in B10113: Diff 17414.Apr 2 2020, 23:17

Fabien accepted this revision.Apr 3 2020, 07:00

This revision is now accepted and ready to land.Apr 3 2020, 07:00

Closed by commit rABC7df20faa1c55: Fix invalid use a memory order relaxed (authored by deadalnix). · Explain WhyApr 3 2020, 13:13

This revision was automatically updated to reflect the committed changes.

deadalnix added a commit: rABC7df20faa1c55: Fix invalid use a memory order relaxed.

deadalnix added a commit: rSTAGING7df20faa1c55: Fix invalid use a memory order relaxed.Apr 7 2020, 23:37

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src/

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Diff 17433

src/net.cpp

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